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Features
* TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family * System Integration Block Including:
Independent Direct Memory Access (IDMA) Controller Interrupt Controller with Two Modes of Operation Parallel Input/output (I/O) Ports, some with Interrupt Capability On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM) Three Timers, including a Watchdog Timer Four Programmable Chip-select Lines with Wait-state Logic Programmable Address Mapping of Dual-port RAM and IMP Registers On-chip Clock Generator with an Output Clock Signal System Control: System Control Register Bus Arbitration Logic with Low Interrupt Latency Support Hardware Watchdog for Monitoring Bus Activity Low Power (Standby) Modes Disable CPU Logic (TS68000) Freeze Control for Debugging Selected On-chip Peripherals DRAM Refresh Controller * Communications Processor Including: - Main Controller (RISC Processor) - Three Full-duplex Serial Communication Controllers (SCCs) - Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs - Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL) General Circuit Interface (GCI, see note), Pulse Code Modulation (PCM), and Nonmultiplexed Serial Interface (NMSI) Operation - Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up to 4.096 MHz - Serial Management Controllers (SMCs) for IDL and GCI Channels * Frequency of Operation: 16.67 MHz * Power Supply: 5 VDC 10% - - - - - - - - -
Integrated Multiprotocol Processor (IMP) TS68302
Description
The IMP is a very large-scale integration (VLSI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications in the communications industry. The IMP is the first device to offer the benefits of a closely coupled, industry-standard, TS68000/TS68008 microprocessor core and a flexible communications architecture. This multichannel communications device may be configured to support a number of popular industry interfaces, including those for the integrated services digital network (ISDN) basic rate and terminal adapter applications. Through a combination of architectural and programmable features, concurrent operation of different protocols is easily achieved using the IMP. Data concentrators, line cards, bridges, and gateways are examples of suitable applications for this versatile device. The IMP is a high-density complementary metal-oxide semiconductor (HCMOS) device consisting of a TS68000/TS68008 microprocessor core, a system integration block (SIB), and a communications processor (CP). The TS68302 block diagram is shown in Figure 1.
Note: GCI is sometimes referred to as IOM2.
Rev. 2117A-HIREL-11/02
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Screening/Quality
This product is manufactured in full compliance with either: * * * MIL-STD-883 (class B) DESC. Drawing 5962-93159 Or according to Atmel standards
R suffix PGA 132 (Ceramic Pin Grid Array)
A suffix CERQUAD 132 (Ceramic Quad Flat Pack)
Introduction
The TS68302 integrated multiprotocol processor (IMP) is a very large-scale integration (VLSI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications in the communications industry. The IMP is the first device to offer the benefits of a closely coupled, industry-standard TS68000 microprocessor core and a flexible communications architecture. The IMP may be configured to support a number of popular industry interfaces, including those for the Integrated Services Digital Network (ISDN) basic rate and terminal adapter applications. Concurrent operation of different protocols is easily achieved through a combination of architectural and programmable features. Data concentrators, line cards, bridges, and gateways are examples of suitable applications for this device. The IMP is a high-density complementary metal-oxide semiconductor (HCMOS) device consisting of a TS68000 microprocessor core, a system integration block (SIB), and a communications processor (CP). Figure 1 is a block diagram of the TS68302. The processor can be divided into two main sections: the bus controller and the micromachine. This division reflects the autonomy with which the sections operate.
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Figure 1. TS68302 Block Diagram
TS68000/TS68008 CORE
TS68000 BUS TS68000/TS68008 CORE
ON-CHIP PERIPHERALS BUS INTERFACE UNIT
INTERRUPT CONTROLLER
BUS ARBITER
1152 BYTES DUAL-PORT STATIC RAM
CHIP-SELECT AND WAITSTATE LOGIC
SYSTEM CONTROL
IDMA (1 CHANNEL)
TIMERS (3)
CLOCK GENERATOR
DRAM REFRESH CONTROLLER
PARALLEL I/O
SYSTEM INTEGRATION BLOCK PERIPHERAL BUS SDMA (6 CHANNELS) SMC (2) SCC1 SCC2 SCC3 SCP
MAIN CONTROLLER (RISC) SERIAL CHANNELS PHYSICAL INTERFACE COMMUNICATIONS PROCESSOR
I/O PORTS AND PIN ASSIGNEMENTS
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Pin Assignments
Figure 2. PGA Terminal Designation
N
PB10 TIN1 IACK1 GND UDS R/W EXTAL VDD IPL1 IPL2 RESET HALT RCLK1
M
CS3 TOUT2 TIN2 VDD IACK7 AS GND CLK0 BERR BR BGACK BG AVEC NC1 RTS3
L
CS2 PB11 GND TOUT1 IACK6 LDS XTAL IPL0 IAC PB9 WDOG PB8
BCLR TCLK1 CD3
K
CS0
RMC
DTACK VDD TXD1 RTS1 BUSW GND BRG1 NC3 DISCPU
J H G F E D C B A
FC2
CS1 GND VDD A3 A4 A8 GND A13 A18 A21
FC0 A1 GND A6 A7 A10 A11 A14
FC1 A2 A5 A9
A12 VDD
TS68302
BOTTOM VIEW
FRZ DONE DACK PA12 DREQ GND TXD3 RCLK3 TCLK3 TXD2 CD2 SDS2 RXD3
A15 GND A20
A16 A23 VDD D14 D13 D11 VDD D10 D8 D9
RXD2 CTS1 TCLK2 GND D4 D5 D7 D1 D2 D6
VDD
A17 A19 A22
CD1 RCLK2 RTS2 D0 GND CTS3 CTS2 D3 RXD1
GND D15
D12 GND
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 3. CERQUAD Terminal Designation
A15 A14 A13 A12 GND A11 A10 A9 A8 A7 A6 A5 A4 GND A3 A2 A1 FC0 VDD FC1 FC2 CS0 CS1 GND CS2 CS3 RMC IAC PB11 PB10 PB9 PB8 WDOG VDD A16 A17 A18 A19 GND A20 A21 A22 A23 VDD GND D15 D14 D13 D12 GND D11 D10 D9 D8 VDD D7 D6 D5 D4 GND D3 D2 D1 D0 CTS3 CD1
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68302 CERQUAD132 (window frame down)
Top VIEW
50
83
GND TOUT2 TIN2 TOUT1 VDD TIN1 IACK1 IACK6 IACK7 GND UDS LDS AS R/W GND XTAL EXTAL VDD CLK0 IPL0 IPL1 IPL2 BERR AVEC RESET HALT BR NC1 BGACK BG BCLR DTACK GND
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CTS1 RXD1 RXD2 TXD2 RCLK2 TCLK2 GND CTS2 RTS2 CD2 SDS2 VDD RXD3 TXD3 RCLK3 TCLK3 GND PA12 DREQ DACK DONE FRZ DISCPU BUSW NC3 BRG1 CD3 RTS3 RTS1 TXD1 TCLK1 RCLK1 VDD
TS68302
Figure 4. Functional Signal Groups
NMSI1/ISDN I/F RXD1/L1RXD TXD1/L1TXD RCLK1/L1CLK TCLK1/L1SY0/SDS1 CD1/L1SY1 CTS1/L1RG RTS1/L1RQ/GCIDCL BRG1 NMSI2/PIO RXD2/PA0 TXD2/PA1 RCLK2/PA2 TCLK2/PA3 CTS2/PA4 RTS2/PA5 CD2/PA6 BRG2/SDS2/PA7 NMSI3/SCP/PIO RXD3/PA8 TXD3/PA9 RCLK3/PA10 TCLK3/PA11 CTS3/SPRXD RTS3/SPTXD CD3/SPCLK BRG3/PA12 IDMA/PAIO DREQ/PA13 DACK/PA14 DONE/PA15 IACK/PBIO IACK7/PB0 IACK6/PB1 IACK1/PB2 TIMER/PBIO TIN/PB3 TOUT1/PB4 TIN2/PB5 TOUT2/ PB6 WDOG/PB7 PBIO (INTERRUPT) PB8 PB9 PB10 PB11 GND(13) V DD (8) TESTING FRZ NC(2) CHIP SELECT CS0/IOUT2 CS3-CS1 TS68302 IMP BUS CONTROL AS R/W UDS/A0 LDS/DS DTACK RMC/IOUT1 IAC BCLR BUS ARBITRATON BR BG BGACK SYSTEM CONTROL RESET HALT BERR BUSW DISCPU INTERRUPT CONTROL IPL0/IRQ1 IPL1/IRQ6 IPL2/IRQ7 FC0 FC1 FC2 AVEC / IOUT0 DATA BUS D15-D0 ADDRESS BUS A23-A1 CLOCKS EXTAL XTAL CLKO
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Signal Descriptions
The input and output signals of the TS68302 are organized into functional groups as shown in Table 1. Refer to TS68302 Integrated Multiprotocol Processor User's Manual, for detailed information on the TS68302 signals.
Table 1. Signal Definitions
Functional Group Clocks System Control Address Bus Data Bus Bus Control Bus Control Bus Arbitration Interrupt Control NMSI1/ISDN I/F NMSI2/PIO NMSI3/SCP/PIO IDMA/PAIO IACK/PBIO Timer/PBIO PBIO Chip Select Testing VDD GND Signals XTAL, EXTAL, CLKO RESET, HALT, BERR, BUSW, DISCPU A23-A1 D15-D0 AS, R/W, UDS/A0, LDS/DS, DTACK RMC, IAC, BCLR BR, BG, BGACK IPL2-IPL0, FC2-FC0, AVEC RXD, TXD, RCLK, TCLK, CD, CTS, RTS, BRG1 RXD, TXD, RCLK, TCLK, CD, CTS, RTS, SDS2 RXD, TXD, RCLK, TCLK, CD, CTS, RTS, PA12 DREQ, DACK, DONE IACK7, IACK6, IACK1 TIN2, TIN1, TOUT2, TOUT1, WDOG PB11-PB8 CS3-CS0 FRZ (2 Spare) Power supply Ground connection Number 3 5 23 16 5 3 3 7 8 8 8 3 3 5 4 4 3 8 13
Scope Applicable Documents
MIL-STD-883
This drawing describes the specific requirements for the processor TS68302, 16.67 MHz, in compliance either with MIL-STD-883 class B or with Atmel standards.
1. MIL-STD-883: test methods and procedures for electronics. 2. MIL-M-38535: general specifications for microcircuits. 3. Desc Drawing: 5962-93159 (planned).
Requirements
General
The microcircuits are in accordance with the applicable document and as specified herein.
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Design and Construction
Terminal Connections Depending on the package, the terminal connections shall be as shown in Figure 2 and Figure 3. Lead material and finish shall be any option of MIL-M-38535. The macrocircuits are packaged in hermetically sealed ceramic packages, which conform to case outlines of MIL-M-38535 appendix A (when defined): * * 132-pin Ceramic Pin Grid Array (PGA), 132-pin Ceramic Quad Flat Pack (CERQUAD).
Lead Material and Finish Package
The precise case outlines are described in Figure 2 and Figure 3.
Electrical Characteristics
Table 2. Absolute Maximum Ratings
Symbol PD PD LPD LPD Parameter Power Dissipation (typical at 16.67 MHz)(1) Power Dissipation (typical at 8 MHz)
(1) (2)
Min 53 26
Max 64 31 36 32
Unit mA mA mA mA
Low Power Mode Dissipation (typical at 16.67 MHz)
Lowest Power Mode Dissipation (typical at 16.67 MHz)(3)
(4)
LPD Lowest Power Mode Dissipation (typical at 50 MHz) 1 mA Notes: 1. The values shown are typical. The typical value varies as shown, based on how many IMP on-chip peripherals are enabled and the rate at which they are clocked. 2. LPREC = 0. Divider = 2. 3. LPREC = 1. Divider = 1024. 4. The stated frequency must be externally applied to EXTAL only after the IMP has been placed in the lowest power mode with LPREC = 1. The 68000 core is not specified to operate at this frequency, but the rest of the IMP is. In this configuration, the user does not divide the clock internally using the LPCD4-LPCD0 bits in the system control register.
Unless otherwise stated, all voltages are referenced to the reference terminal (see Table 1). Table 3. Recommended Condition of Use
Symbol VCC VIL VIH Tcase tr(c) tf(c) fc tcyc Parameter Supply Voltage Low Level Input Voltage High Level Input Voltage Operating Temperature Clock Rise Time - See Figure 5 Clock Fall Time Resistance - Figure 5 Clock Frequency - See Figure 5 Cycle Time - See Figure 5 8 60 Min 4.5 -0.3 2.4 -55 Max 5.5 +0.5 5.5 +125 5 5 16.67 125 Unit V V V C ns ns MHz ns
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This device contains protective circuitry to protect the inputs against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VDD). Figure 5. Clock Input Timing Diagram
tcyc
2.0V
0.8V tr (C)
Note:
tf (C)
Timing measurements are referenced to and from a low voltage of 0.8V and a voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside, and pass through, the range such that the rise or fall will be linear between 0.8V and 2.0V.
Table 4. Thermal Characteristics at 25C
Package PGA 132 CERQUAD 132 Symbol JA JC JA JC Parameter Thermal Resistance - Ceramic Junction To Ambient Thermal Resistance - Ceramic Junction To Case Thermal Resistance - Ceramic Junction To Ambient Thermal Resistance - Ceramic Junction To Case Value 33 5 46 2 Unit C/W C/W C/W C/W
Power Considerations
The average chip-junction temperature, TJ, in C can be obtained from: TJ = TA + (PD JA) TA = Ambient Temperature, C (1)
JA = Package Thermal Resistance, Junction-to-Ambient, C/W
PD = PINT + PI/O PINT = ICC VCC, Watts - Chip Internal Power PI/O = Power Dissipation on Input and Output pins - user determined
Note: For TA = 70C and PD = 0.5 W at 12.5 MHz Tj = 88C.
For most applications PI/O < 0,30 PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273) Solving equations (1) and (2) for K gives: K = PD (TA + 273) + JA PD2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P D (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (2)
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The total thermal resistance of a package (JA) can be separated into two components, JC and CA, representing the barrier to heat flow from the semiconductor junction to the package (case), surface (JC) and from the case to the outside ambient (CA). These terms are related by the equation:
JA = JC + CA
(4)
JC is device-related and cannot be influenced by the user. However, CA is user-dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal convection. Thus, good thermal management on the part of the user can significantly reduce CA so that JA approximately equals JC. Substitution of JC for JA in equation (1) will result in a lower semiconductor junction temperature.
Mechanical and Environment Marking
The microcircuits shall meet all mechanical environmental requirements of either MILSTD-883 for class B devices or Atmel standards. The document that defines the marking is identified in the related reference documents. Each microcircuit is legible and permanently marked with the following information as minimum: * * * * * * Atmel Logo Manufacturer's part number Class B identification Date-code of inspection lot ESD identifier if available Country of manufacturing
Quality Conformance Inspection
DESC/MIL-STD-883
Those quality levels are in accordance with MIL-M-38535 and method 5005 of MILSTD-883. Groups A and B inspections are performed on each production lot. Groups C and D inspection are performed on a periodical basis.
Electrical Characteristics
General Requirements
All static and dynamic electrical characteristics specified. For inspection purposes, refer to relevant specification: * DESC see "DESC/MIL-STD-883" on page 9 Table 5 and Table 6: Static Electrical Characteristics for all electrical variants. Test methods refer to IEC 748-2 method number, where existing. Table 7 and Table 8: Dynamic Electrical Characteristics. Test methods refer to this specification.
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Table 5. DC Electrical Characteristics VCC = 5.0 Vdc 10%; GND = 0 Vdc; Tc = -55C/+125C or -40C/+85C
Symbol VIH VIL VCIH VCIL IIN CIN ITSI IOD VOH VOL Parameter Input High Voltage (except EXTAL) Input Low Voltage (except EXTAL) Input High Voltage (EXTAL) Input Low Voltage (EXTAL) Input Leakage Current Input Capacitance All Pins Three-state Leakage Current (2.4V/0.5V) Open Drain Leakage Current (2.4V) Output High Voltage (IOH = 400 A) Output Low Voltage (IOL = 3.2 mA) A1-A23, PB0-PB11, FC0-FC3, CS0-CS3, IAC, AVEC, BG, RCLK1, RCLK2, RCLK3, TCLK1, TCLK2, TCLK3, RTS1, RTS2, RTS3, SDS2, PA12, RXD2, RXD3, CTS2, CD2, CD3, DREQ AS, UDS, LDS, R/W, BERR, BGACK, BCLR, DTACK, DACK, RMC, RMC, D0-D15, RESET TXD1, TXD2, TXD3 BR, DONE, HALT, (BR as output) CLKO 0.5 V VDD - 1.0 Min 2.0 VSS - 0.3 4.0 VSS - 0.3 Max VDD 0.8 VDD 0.6 20 15 20 20 Unit V V V V A pF A A V
(IOL = 5.3 mA) (IOL = 7.0 mA) (IOL = 8.9 mA) (IOL = 3.2 mA) OCLK OGCI OALL
0.5 0.5 0.5 0.4 50 150 130
V V V V pF pF pF
Output Drive CLKO Output Drive ISDN I/F (GCI mode) Output Drive All Other Pins
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Table 6. DC Electrical Characteristics - NMSI1 in IDL mode
Symbol VDD VSS T Parameter Power Common Temperature Operating range Condition Min 4.5 0 -55 Nom 5.0 0 25 Max 5.5 0 +125 Unit V V C
Input Pin Characteristics: L1CLK, L1SY1, L1R x D, L1GR VIL VIH IIH IIH Input Low Level Voltage Input High Level Voltage Input Low Level Current Input High Level Current Vin = VSS Vin = VDD (% of VDD) -10% VDD - 20% +20% VDD + 10% 10 10 V V A A
Output Pin Characteristics: L1T x D, SDS1-SDS2, L1RQ VOL VOH Output Low Level Voltage Output High Level Voltage IOL = 2.0 mA IOH = 2.0 mA 0 VDD - 0.5 0.50 VDD V V
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Dynamic (Switching) Characteristics
The limits and values given in this section apply over the full case temperature range 55C to +125C or -40C to +85C depending on selection see "Ordering Information" on page Reference 2 and VCC in the range 4.5V to 5.5V VIL = 0.5V and VIH = 2.4V. The INTERVAL numbers (NUM) refer to the timing diagrams. See Figure 6 to Figure 25. The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the clock (CLKO pin) and possibly to one or more other signals.
Figure 6. Clock Timing Diagram
1 VCIH = 4V EXTAL 3 VCIL = 0.6V 5 5a CLKO 4 5a 2
Table 7. AC Electrical Specifications - Clock Timing (see Figure 7)
Num. Symbol f 1 2, 3 4, 5 tcyc tCL, tCH tCr, tCf Parameter Frequency of Operation Clock Period (EXTAL) Clock Pulse Width (EXTAL) Clock Rise and Fall Times (EXTAL)
(1)(2)
Min 8 60 25
Max 16.67 125 62.5 5
Unit MHz ns ns ns
5a tCD EXTAL to CLKO delay 2 11 ns Notes: 1. CLKO loading is 50 pF max. 2. CLKO skew from the rising and falling edges of EXTAL will not differ from each other more than 1 ns, if the EXTAL rise time equals the EXTAL fall time.
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Table 8. AC Electrical Specifications IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 9) f = 16.67 MHz
Num. 6 7 8 9 11 12 13 14 14A 15 16 17 18 20 20A 21 22 23 25 26 27 28 29 30 31 32 33 34 35 36 37 37A 38 39 Symbol tCHFCADV tCHADZ tCHAFI tCHSL tAFCVSL tCLSH tSHAFI tSL tDSL tSH tCHCZ tSHRH tCHRH tCHRL tASRV tAFCVRL tRLSL tCLDO tSHDOI tDOSL tDICL tSHDAH tSHDII tSHBEH tDALDI tRHr, tRHf tCHGL tCHGH tBRLGL tBRHGH tGALGH tGALBRH tGLZ tGH Parameter Clock high to FC, address valid Clock high to address, data bus high impedance (maximum) Clock high to address, FC invalid (minimum) Clock high to AS, DS asserted(1) Address, FC valid to AS, DS asserted (read)/AS asserted (write)(2) Clock low to AS, DS negated(1) AS, DS negated to address, FC invalid AS (and DS read) width asserted DS width asserted, write(2) AS, DS width negated
(2) (2) (2)
Min
Max 45 50
Unit ns ns ns
0 3 15 30 15 120 60 60 50 15 30 30 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Clock high to control bus high impedance AS, DS negated to R/W invalid Clock high to R/W high(1) Clock high to R/W low
(1) (2)(3) (2) (2)
AS asserted to R/W low (write)
10 15 30 30
(2)
Address FC valid to R/W low (write) R/W low to DS asserted (write)(2) Clock low to data-out valid
ns ns ns ns
AS, DS, negated to data-out invalid (write) Data-out valid to DS asserted (write)
(2)
15 15 7
(2)
Data-in valid to clock low (Setup time on read)(4) AS, DS negated to DTACK negated (asynchronous hold) AS, DS negated to data-in invalid (hold time on read) AS, DS negated to BEER negated DTACK asserted to data-in valid (setup time)(2)(4) HALT and RESET input transition time Clock high to BG asserted Clock high to BG negated BR asserted to BG asserted BR negated to BG negated(5) BGACK asserted to BG negated BGACK asserted to BG negated
(6)
0 0 0
110
ns ns ns
50 150 30 30 2.5 1.5 2.5 10 4.5 2.5 4.5 1.5 50 1.5
ns ns ns ns clks clks clks ns/clks ns clks
BG asserted to control, address, data bus high impedance (AS negated) BG width negated
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Table 8. AC Electrical Specifications IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 9) f = 16.67 MHz (Continued)
Num. 44 46 47 48 53 55 56 57 57A 58 58A 60 61 62 63 64 Notes: 1. 2. 3. 4. Symbol tSHVPH tGAL tASI tBELDAL tCHDOI tRLDBD tHRPW tGASD tGAFD fRHSD tRHFD tCHBCL tCHBCH tCLRML tCHRMH Parameter AS, DS negated to AVEC negated BGACK width low Asynchronous input setup time
(4)
Min 0 1.5 10 10 0 0 10 1.5 1
(5)
Max 50
Unit ns clks ns ns ns ns clks clks clks clks clks
BERR asserted to DTACK asserted(2)(7) Data-out hold from clock high R/W asserted to data bus impedance change HALT/RESET pulse width
(8)
BGACK negated to AS, DS, R/W driven BGACK negated to FC BR negated to AS, DS, R/W driven BR negated to FC
(5)
1.5 1 30 30 30 30
Clock high to BCLR asserted Clock high to BCLR negated
(9)
ns ns ns ns
Clock low (S0 falling edge during read) to RMC asserted Clock high (S7 rising edge during write) to RMC negated
tRMHGL RMC negated to BG asserted(10) 30 ns For loading capacitance of less than or equal to 50 pF, subtract 4 ns from the value given in the maximum columns. Actual value depends on clock period. When AS and R/W are equally loaded (20%), subtract 5 ns from the values given in these columns. If the asynchronous input setup (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. 5. The TS68302 will negate BG and begin driving the bus if external arbitration logic negates BR before asserting BGACK. 6. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted. 7. If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is a synchronous input using the asynchronous input setup time (#47). 8. For power-up, the TS68302 must be held in the reset state for 100 ms to allow stabilization of on-chip circuit. After the system is powered up #56 refers to the minimum pulse width required to reset the processor. 9. Occurs on S0 of SDMA read/write access when the SDMA becomes bus master. 10. This specification is valid only when the RMCST bit is set in the SCR register.
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Figure 7. Read Cycle Timing Diagram
S0 CLKO S1 S2 S3 S4 S5 S6 S7
FC2-FC0 8 6 A23-A1 7 14 AS 15 13 9 11 LDS-UDS 17 18 R/W 12
47 DTACK 48 31 DATA IN 27
28
29
47 BERR/BR (Note 2) 47 32 HALT / RESET 56 47 ASYNCHRONOUS INPUTS (Note 1) 32 47
30
Notes:
1. Setup time for asynchronous inputs IPL2-IPL0 guarantees their recognition at the next falling edge of the clock. 2. BR needs to fall at this time only to ensure being recognized at the end of the bus cycle. 3. Timing measurements are reinforced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8V and 2.0V.
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Figure 8. Write Cycle Timing Diagram
OUT
Notes:
1. Timing measurements are referenced to and from a low voltage of 0.8V and a high of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise and fall is linear between 0.8V and 2.0V. 2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge of S2 (specification #20A).
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Figure 9. Bus Arbitration Timing Diagram
STROBES AND R/W
36 37A
BR
37 46 57 57A
BGACK
47 35 34 39 58 58A
BG
33 38 CLKO
Note:
Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, and IPL2-IPL0 guarantees their recognition at the next falling edge of the clock.
Table 9. AC Electrical Specifications - DMA (see Figure 10) f = 16.67 MHz
Num. 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Notes: 1. 2. 3. 4. Symbol tREQASI tREQL tREQLBRL tCHBRL tCHBRZ tBKLBRZ tCHBKL tABHBKL tBGLBKL tBRHBGH tCLBKLAL tCHBKH tCLBKZ tCHACKL tCLACKH tCHDNL tCLDNZ Parameter DREQ asynchronous setup time(1) DREQ width low
(2) (3)(4)
Min 15 2
Max
Unit ns clk
DREQ low to BR low Clock high to BR low
2 30 30 30 30 1.5 2.5 + 30 2.5 + 30 0 2 2 30 15 30 30 30 30 15
clk ns ns ns ns clk ns clk ns ns clk ns ns ns ns ns ns ns
(3)(4)
Clock high to BR high impedance(3)(4) BGACK low to BR high impedance Clock high to BGACK low AS and BGACK high (the latest one) to BGACK low (when BG is asserted) AS low to BGACK low (no other bus master)(3)(4) BR high impedance to BG high(3)(4) Clock on which BGACK low to clock on which AS low Clock high to BGACK high Clock low to BGACK high impedance Clock high to DACK low Clock high to DACK high Clock high to DONE low (output) Clock low to DONE high impedance
(3)(4)
tDNLTCH DONE input low to clock high (asynchronous setup) is sampled on the falling edge of CLK in cycle steal and burst modes. DREQ If #80 is satisfied for DREQ, #81 may be ignored. BR will not be asserted while AS, HALT, or BERR is asserted. Specifications are for DISABLE CPU mode only.
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Figure 10. DMA Timing Diagram
Table 10. AC Electrical Specifications - External Master Internal Asynchronous Read/write Cycles(2) f = 16.67 MHz
Num. 100 101 102 103 104 105 106 107 108 108A 109 Symbol tRWVDSL tDSLDIV tDKLDH tASVDSL tDKLDSH tDSHDKH tDSIASI tDSHRWH tDSHDZ tDSHDH tDSHDOH Parameter R/W valid to DS low DS low to data in valid DTACK low to data in hold time AS valid to DS low DTACK low to DS high DS high to DTACK high DS inactive to AS inactive DS high to R/W high DS high to data high impedance DS high to data out hold time DS high to data in hold time(1) 0 0 0 0 45 0 0 0 45 Min 0 30 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
109A tDOVDKL Data out valid to DTACK low 15 Note: 1. If AS is negated before DS, the data bus could be three-stated (spec 126) before DS is negated. 2. See Figure 11 and Figure 12.
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Figure 11. External Master Internal Asynchronous Read Cycle Timing Diagram
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Figure 12. External Master Internal Asynchronous Write Cycle Timing Diagram
Table 11. AC Electrical Specifications(2) External Master Internal Synchronous Read/write Cycles(1) f = 16.67 MHz
Num. 110 111 112 113 114 115 116 117 118 119 120 121 122 Symbol tAVASL tASLCH tCLASH tASHAH tASH tSLCH tCLSH tRWVCH tCHRWH tASLIAH tASHIAL tASLDTL tCLDTL Parameter Address valid to AS low AS low to clock high Clock low as to AS high AS high to address hold time on write AS inactive time UDS/LDS low to clock high Clock low to UDS/LDS high R/W valid to clock high Clock high to R/W high AS low to IAC high AS high to IAC low AS low to DTACK low (0 wait state) Clock low to DTACK low (1 wait state) 30 45 40 40 45 30 0 1 40 45 Min 15 30 45 Max Unit ns ns ns ns clk ns ns ns ns ns ns ns ns
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Table 11. AC Electrical Specifications(2) External Master Internal Synchronous Read/write Cycles(1) f = 16.67 MHz (Continued)
Num. 123 124 125 126 127 128 129 130 Symbol tASHDTH tDTHDTZ tCHDOV tASHDZ tASHDOI tASHAI tSH tCLDIV Parameter AS high to DTACK high DTACK high to DTACK high impedance Clock high to data out valid AS high to data high impedance AS high to data out hold time AS high to address hold time on read UDS/LDS inactive time Data in valid to clock low 0 0 1 30 15 Min Max 45 15 30 45 Unit ns ns ns ns ns ns clk ns ns
131 tCLDIH Clock low to data in hold time Notes: 1. See Figure 13, Figure 14 and Figure 15. 2. Specifications are valid only when SAM = 1 in the SCR.
Figure 13. External Master Internal Synchronous Read Cycle Timing Diagram
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Figure 14. External Master Internal Synchronous Read Cycle Timing Diagram (One Wait State)
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Figure 15. External Master Internal Synchronous Write Cycle Timing Diagram
Table 12. AC Electrical Specifications - Internal Master Read/write Cycles(1) f = 16.67 MHz
Num. 140 141 142 143 144 145 Note: Symbol tCHIAH tCLIAL tCHDTL tCLDTH tCHDOV tASHDOH 1. See Figure 16. Parameter Clock high to IAC high Clock low to IAC low Clock high to DTACK low (0 wait state) Clock low to DTACK high Clock high to data out valid AS high to data out hold time 0 Min Max 40 40 45 40 30 Unit ns ns ns ns ns ns
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Figure 16. Internal Master Internal Read Cycle Timing Diagram
S0 CLKO (OUTPUT) S1 S2 S3 S4 S5 S6 S7 S0
A23-A1 (OUTPUT)
AS (OUTPUT) 140 IAC (OUTPUT) 141
UDS LDS (OUTPUT)
R/W (OUTPUT) D15-D0 (OUTPUT) 142 DTACK (OUTPUT)
144
145
143
Table 13. AC Electrical Specifications - Chip-select Timing Internal Master(3) f = 16.67 MHz
Num. 150 151 152 153 154 155 156 157 158 171 172 173 174 175 Symbol tCHCSIAKL tCLCSIAKH tCSH tCHDTKL tCLDTKL tCLDTKH tCHBERL tCLBERH tDTKHDTKZ tIDHCL tCSNDOI tAFVCSA tCSNAFI tCSLT Parameter Clock high to CS, IACK low
(1)
Min
Max 40 40
Unit ns ns ns
Clock low to CS, IACK high(1) CS width negated Clock high to DTACK low (0 wait state) Clock low to DTACK low (1 - 6 wait states) Clock low to DTACK high Clock high to BERR low(2) Clock low to BERR high impedance
(2)
60 45 30 40 40 40 15 5
(4)
ns ns ns ns ns ns ns ns ns ns ns
DTACK high to DTACK high impedance Input data hold time from S6 low CS negated to data out invalid (write) Address, FC valid to CS asserted
(4) (4)
10 15 15 120
CS negated to address, FC invalid CS low time (0 wait states)(4)
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Table 13. AC Electrical Specifications - Chip-select Timing Internal Master(3) f = 16.67 MHz (Continued)
Num. 176 177 178 Notes: 1. 2. 3. 4. Symbol tCSNRWI tCSARWL Parameter CS negated to R/W invalid
(4) (4) (4)
Min 10
Max
Unit ns
CS asserted to R/W low (write)
10
ns
tCSNDII CS negated to data in invalid (hold time on read) 0 ns For loading capacitance less than or equal to 50 pF, subtract 4 ns from the maximum value given. This specification is valid only when the ADCE or WPVE bits in the SCR are set. See Figure 17. Specs 172-178 do not have diagrams. However, similar diagrams for AS are shown as 25-11-13-14-17-20A and 29.
Figure 17. Internal Master Chip-select Timing Diagram
S0 CLKO (OUTPUT) 152 150 CS0-CS3 IACK1,IACK6, IACK7 (OUTPUT) 151 S1 S2 S3 S4 S5 S6 S7 S0 Sw Sw S4 S5 S6 S7 S0
158 153 155 154
DTACK (OUTPUT) 156 BERR (OUTPUT) 157
Table 14. AC Electrical Specifications - Chip-select Timing External Master(4) f = 16.67 MHz
Num. 154 160 161 162 163 164 165 167 168 169 Notes: 1. 2. 3. 4. Symbol tCLDTKL tASLCSL tASHCSH tAVASL tRWVASL tASHAI tASLDTKL tASHDTKH tASLBERL Parameter Clock low to DTACK low (1-6 wait states) AS low to CS low AS high to CS high Address valid to AS Low R/W valid to AS Low
(1)
Min
Max 30 30 30
Unit ns ns ns ns ns ns
15 15 0 45 30 30 30
AS negated to Address hold time AS low to DTACK low (0 wait state) AS high to DTACK high AS low to BERR low
(2) (2)(3)
ns ns ns ns
tASHBERH AS high to BERR high The minimum value must be met to guarantee write protection operation. This specification is valid when the DCE or WPVE bits in the SCR are set. Also applies after a timeout of the hardware watchdog. See Figure 18
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Figure 18. External Master Chip-select Timing Diagram
S0 CLKO A23-A1 (INPUT) 162 AS (INPUT) 160 CS3-CS0 (OUTPUT) 163 R/W (INPUT) 167 158 165 DTACK (OUTPUT) 168 BERR (OUTPUT)
169
S1
S2
S3
S4
S5
S6
S7
S0
164
161
Table 15. AC Electrical Specifications - Parallel I/O(1) f = 16.67 MHz
Num. 180 181 182 Note: Symbol tDSU tDH tCHDOV 1. See Figure 19 Parameter Input Data Setup Time (to clock low) Input Data Hold Time (from clock low) Clock High to Data Out Valid (CPU writes data, control, or direction) 35 Min 20 10 35 Max Unit ns ns ns
Figure 19. Parallel I/O Data In/data Out Timing Diagram
CLKO
DATA IN
180 181
DATA OUT
182
CPU WRITE S6
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Table 16. AC Electrical Specifications - Interrupts(2) f = 16.67 MHz
Num. 190 Symbol tIPW Parameter Interrupt pulse width low IRQ (edge triggered mode) Min 50 Max Unit ns
191 tAEMT Minimum time between active edges 3 clk Note: 1. Set up time for the asynchronous inputs IPL2-IPL0 and AVEC guarantees their recognition at the next falling edge of the clock. 2. See Figure 20.
Figure 20. Interrupts Timing Diagram
IRQ (INPUT) 190 191
Table 17. AC Electrical Specifications - Timers(2) f = 16.67 MHz
Num. 200 201 202 203 204 205 Symbol tTPW tTICLT tTICHT tcyc tCHTOV tFRZSU Parameter Timer input capture pulse width TIN clock low pulse width TIN clock high pulse width TIN clock cycle time Clock high to TOUT valid FRZ input setup time (to clock high)
(1)
Min 50 50 2 3
Max
Unit ns ns clk clk
35 20 10
ns ns ns
206 tFRZHT FRZ input hold time (from clock high) Note: 1. FRZ should be negated during total system reset. 2. See Figure 21.
Figure 21. Timers Timing Diagram
CLKO
TOUT (OUTPUT) 204 TIN (INPUT) 201 203 FRZ (INPUT) 200 202 205 206
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Table 18. AC Electrical Specifications - Serial Communication Port(2) f = 16.67 MHz
Num. 250 251 252 253 Parameter SPCLK clock output period SPCLK clock output rise/fall time Delay from SPCLK to transmit SCP receive setup time(1)
(1) (1)
Min 4
Max 64 15
Unit clks ns ns ns
0 40
40
254 SPC receive hold time 10 ns Note: 1. This also applies when SPCLK is inverted by CI in the SPMODE register. The enable signals for the slaves may be implemented by the parallel I/O pins. 2. See Figure 22.
Figure 22. Serial Communication Port Timing Diagram
250 251
SPCLK (OUTPUT)
252
SPTXD (OUTPUT)
1
2
3
4
253
5
6
7
8
254
SPRXD (INPUT)
1
2
3
4
5
6
7
8
Table 19. AC Electrical Specifications - Idle Timing(3) f = 16.67 MHz All timing measurements, unless otherwise specified, are referenced to the L1CLK at 50% point of VDD
Num. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 Parameter L1CLK (IDL clock) frequency L1CLK width low L1CLK width high L1T x D, L1RQ, SDS1-SDS2 rising/falling time L1SY1 (sync) setup time (to L1CLK falling edge) L1SY1 (sync) hold time (to L1CLK falling edge) L1SY1 (sync) inactive before 4th L1CLK L1T x D active delay (from L1CLK rising edge) L1T x D to high impedance (from L1CLK rising edge) L1R x D setup time (to L1CLK falling edge) L1R x D hold time (from L1CLK falling edge) Time between successive IDL syncs L1RQ valid before falling edge of L1SY1 L1GR setup time (to L1SY1 falling edge)
(2) (1)
Min
Max 6.66
Unit MHz ns ns
55 60 20 30 50 0 0 0 50 50 20 1 50 75 50
ns ns ns ns ns ns ns ns L1CLK L1CLK ns
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Table 19. AC Electrical Specifications - Idle Timing(3) f = 16.67 MHz All timing measurements, unless otherwise specified, are referenced to the L1CLK at 50% point of VDD (Continued)
Num. 274 275 276 Notes: 1. 2. 3. Parameter L1GR hold time (from L1SY1 falling edge) SDS1-SDS2 active delay from L1CLK rising edge Min 50 10 75 Max Unit ns ns
SDS1-SDS2 inactive delay from L1CLK falling edge 10 75 ns The ratio CLK/L1CLK must be greater than 2.5/1. High impedance is measured at the 30% and 70% of VDD points, with the line at VDD/2 through 10K in parallel with 130 pF. See Figure 23.
Figure 23. IDL Timing Diagram
271 265 L1SY1 (INPUT) 264 260 262 L1CLK (INPUT) 266
1
2
3 261
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
267 L1TXD (OUTPUT) 270 269 L1RXD (INPUT) B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 268 B26 B25 B24 B23 B22 B21 B20 D2 M
263
275 SDS1 SDS2 (OUTPUT) 272 L1RQ (OUTPUT) 273 274 L1GR (INPUT)
276
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Table 20. AC Electrical Specifications - GCI Timing(5) f = 16.67 MHz GCI supports the NORMAL mode and the GCI channel 0 (GCN0) in MUX mode. Normal mode uses 512 kHz clock rate (256K bit rate). MUX mode uses 256 x n - 3068K bits/sec (clock rate is data rate x 2). The ratio CLK/L1CLK must be greater than 2.5/1.
Num. Parameter L1CLK GCI clock frequency (normal mode) 280 281 282 L1CLK clock period normal mode(1) L1CLK width low/high normal mode L1CLK rise/fall time normal mode
(2) (1) (1)
Min
Max 512
Unit kHz ns ns ns MHz ns ns
1800 840 -
2100 1450 6.668
L1CLK (GCI clock) period (MUX mode) 280 281 282 283 284 285 286 287 288 289 290 291 292 293 Notes: 1. 2. 3. 4. 5. L1CLK clock period MUX mode(1) L1CLK width low/high MUX mode L1CLK rise/fall time MUX mode
(2)
150 55 30 50 0 0 20 50 64 192 10 10 10 90 90 90 100 100 -
ns ns ns ns ns ns ns L1CLK L1CLK ns ns ns ns
L1SY1 sync setup time to L1CLK falling edge L1SY1 sync hold time from L1CLK falling edge L1T x D active delay (from L1CLK rising edge) L1T x D active delay (from L1SY1 rising edge) L1R x D setup time to L1CLK rising edge L1R x D hold time from L1CLK rising edge Time between successive L1SY1 in normal mode SCIT mode SDS1-SDS2 active delay from L1CLK riding edge(4) SDS1-SDS2 active delay from L1SY1 rising edge
(4) (3)
(3)
SDS1-SDS2 inactive delay from L1CLK falling edge
GCIDCL (GCI Data clock) active delay 0 50 The ratio CLK/L1CLK must be greater than 2.5/1. Schmitt trigger used on input buffer. Condition CL = 150 pF. L1T x D becomes valid after the L1CLK rising edge or L1SY1, whichever is later. SDS1-SDS2 become valid after the L1CLK rising edge or L1SY1, whichever is later. See Figure 24.
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Figure 24. GSI Timing Diagram
Table 21. AC Electrical Specifications - PCM Timing(4) f = 16.67 MHz There are two sync types: Short frame - Sync signals are one clock cycle prior to the data. Long frame - Sync signals are N-bits that envelope the data, N > 0.
Num. 300 301 302 303 304 305 306 307 308 309 310 311 Notes: 1. 2. 3. 4. Parameter L1CLK (PCM clock) frequency L1CLK width low/high L1SY0-L1SY1 setup time to L1CLK falling edge L1SY0-L1SY1 hold time from L1CLK falling edge L1SY0-L1SY1 width low Time between successive sync signals (short frame) L1T x D data valid after L1CLK rising edge
(2) (1)
Min
Max 6.66
Unit MHz ns ns ns L1CLK L1CLK
55 20 40 1 8 0 0 20 50 0 100 70 50
ns ns ns ns ns
L1T x D to high impedance (from L1CLK rising edge) L1R x D setup time (to L1CLK falling edge)
(3)
L1R x D hold time (from L1CLK falling edge)(3) L1T x D data valid after syncs rising edge (long)(2)
L1T x D to high impedance (from L1SY0-L1SY1 falling edge) (long) 0 70 ns The ratio CLK/TCLK1 must be greater than 2.5/1. L1T x D becomes valid after the L1CLK rising edge or the sync enable, whichever is later, if long frames are used. Specification valid for both sync methods. See Figure 25.
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Table 22. AC Electrical Specifications - NMSI Timing(4) The NMSI mode uses two clocks, one for receive and one for transmit. Both clocks can be internal or external. When the clock is internal, it is generated by the internal baud rate generator and it is output on L1R x D or L1T x D. All the timing is related to the external clock pin. The timing is specified for NMSI1. It is also valid for NMS12 and NMS13.
Internal Clock Num. 315 316 317 318 319 320 321 322 Parameter RCLK1 and TCLK1 frequency(1) RCLK1 and TCLK1 low/high RCLK1 and TCLK1 rise/fall time
(2)
External Clock Min Max 6.668 55 Unit MHz ns -- 70 100 ns ns ns ns ns ns
Min
Max 5.12
70 -- 0 0 50 50
(3)
-- 40 40
-- 0 0 10 10 50
T x D1 active delay TCLK1 falling edge RTS1 active/inactive delay from TCLK1 falling edge CTS1 setup time to TCLK1 rising edge R x D1 setup time to RCLK1 rising edge R x D1 hold time from RCLK1 rising edge
10
323 CD1 setup time to RCLK1 rising edge 50 10 ns Notes: 1. The ratio CLK/TCLK1 and CLK/RCLK1 must be greater than 2.5/1 for external clock. For internal clock the ratio must be greater than 3/1 (the input clock to the baud rate generator may be either CLK or TIM1), in both cases the maximum frequency is limited to 16.67 MHz. In asynchronous mode (UART), the bit rate is 1/16 of the clock rate. 2. Schmitt triggers used on input buffers. 3. Also applies to CD hold time when CD is used as an external sync in BISYNC or totally transparent mode. 4. See Figure 26.
Figure 25. PCM Timing Diagram
L1CLK (INPUT) 302 300 L1SY0 L1SY1 (INPUT) 304 305 306 L1TXD (OUTPUT) 308 L1RXD (INTPUT) 302 L1SY0 L1SY1 (INPUT) 310 L1TXD (OUTPUT) 1 2 3 4 5 6 7 8 9 307 1 2 3 4 5 6 7 8 303 SYNC ENVELOPES DATAS 311 9 1 2 309 3 4 5 6 7 307 8 1 2 3 301 4 5 6 7 8 9 10 11
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Figure 26. NMSI Timing Diagram
316 317 317
RCLK1
315 321
RXD1 (INPUT)
322 323
CD1 (INPUT)
322
CD1 (SYNC INPUT)
316 317 317
TCLK1
315 318
TXD1 (OUTPUT)
319 319
RTS1 (OUTPUT)
320
CTS1 (INPUT)
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Functional Description
The TS68302 uses a microprocessor architecture which has peripheral devices connected to the system bus through a dual-port memory. Various parameters, counters, and all memory buffer descriptor tables reside in the dual-port RAM. The receive and transmit data buffer may be located in this on-chip RAM or in the off-chip system RAM (see Figure 29). Six DMA channels are dedicated to the six serial ports (receive and transmit for each of the three SCC channels). If an SCC channel's data is programmed to be located in the external RAM, the CP main controller (RISC processor) will program the corresponding DMA channel to perform the required accesses. If the data resides in the on-chip dual-port RAM, then the CP main controller accesses the RAM with one clock cycle access and no arbitration delays. The buffer memory structure of the TS68302 can be configured by the software to closely match I/O channel requirements. The interrupt structure is also programmable to relieve the on-chip 68000/68008 core from bit manipulation functions for peripherals, allowing the processor to perform application software or protocol processing. In some cases, the interface to equipment or proprietary networks may require the use of standard control and data signals. For these signals, the TS68302 can be programmed to use the NMSI mode. This mode is available for one, two, or all three SCC ports; remaining ports may then use one of the multiplexed interface modes: IDL, GCI, or PCM.
Figure 27. Buffer Memory Structure
DUAL-PORT RAM (1152 BYTES) EXTERNAL MEMORY
TX BUFFER DESCRIPTORS (8) SYSTEM RAM (576 BYTES) TX DATA BUFFER
FRAME STATUS DATA LENGTH DATA POINTER TX DATA BUFFER
RX BUFFER DESCRIPTORS (8) SCC1 BUFFER DESCRIPTORS TABLE
PARAMETER RAM (576 BYTES)
FRAME STATUS SCC2 BUFFER DESCRIPTORS TABLE DATA COUT RX DATA BUFFER DATA POINTER
SCC3 BUFFER DESCRIPTORS TABLE
D
DATA
SCP DESCRIPTOR
SMC1 DESCRIPTOR
E
TX DATA
SMC2 DESCRIPTOR
R
RX DATA
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68000/68008 Core Overview
The TS68302 allows operation either in the full 68000 mode with a 16-bit data bus or in the 68008 mode with an 8-bit data bus.
System Integration Block The TS68302 has an SIB which simplifies the task of hardware and software design. The IDMA controller eliminates the need for an external DMA controller on the system (SIB)
board. In addition, there is an interrupt controller that can be used in a dedicated mode to generate interrupt acknowledge signals without external logic. Similarly, the chipselect signals and wait-state logic eliminate the need to generate these signals externally. The SIB includes the IDMA controller, interrupt controller, parallel I/O ports, dual-port RAM, three timers, chip-select logic, clock generator, and system control. IDMA Controller The TS68302 has one IDMA channel and six serial DMA channels which operate concurrently with other CPU operations. The IDMA can operate in different modes of data transfer as programmed by the user. The six serial DMA channels for the three fullduplex SCC channels are transparent to the user, implementing bus-cycle-stealing data transfers controlled by the TS68302's internal RISC controller. These six channels have priority over the separate IDMA channels. The IDMA controller can transfer data between any combination of memory and I/O devices. In addition, data may be transferred in either byte or word quantities, and the source and destination addresses may be either odd or even. Every IDMA cycle requires between two and four bus cycles, depending on the address boundary and transfer size. If both the source and destination addresses are even, the IDMA fetches one word of data and then immediately deposits it. If either the source or destination block begins on an odd boundary, the transfer takes more bus cycles. The IDMA features are as follows: * * * * * * * * * Interrupt Controller memory-memory, memory-peripheral, or peripheral-memory data transfers, operation with data blocks located at even or odd addresses, packing and unpacking of operands, fast transfer rates: up to 4 MBps at 16 MHz with no wait states, full support of all bus exceptions: halt, bus error, and retry, flexible request generation two address pointer registers and one counter register, three I/O lines for externally requested data transfers, asynchronous bus structure with 24-bit address and 8- to 16-bit data bus.
The interrupt controller, which manages the priority of internal and external interrupt requests, generates a vector number during the CPU interrupt acknowledge cycle. Nested interrupts are fully supported. The interrupt controller receives requests from internal sources (INRQ interrupts) such as the timers, the IDMA, the serial controllers, and the parallel I/O pins (port B). The interrupt controller allows the masking of each INRQ interrupt source. When multiple events within a peripheral can cause the interrupt, each of these events is also maskable.
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Figure 28. Interrupt Controller Block Diagram
TIMERS SCP SMCs DMA PB8-PB11 3 1 2 2 4 INTERRUPT IN-SERVICE REGISTER (ISR) IRQ7/ IPL0 IRQ6/ IPL1 IRQ1/ IPL2
INTERRUPT PENDING REGISTER (IPR)
SCC1 EVENT REGISTER 1
INTERRUPT MASK REGISTER (IMR)
SCC1 MASK REGISTER
INTERRUPT PRIORITY RESOLVER
SCC2 EVENT REGISTER SCC2 MASK REGISTER 1
IPL2-IPL0 TO TS68000 CORE
SCC3 EVENT REGISTER SCC3 MASK REGISTER 1
IACK1 VECTOR GENERATION LOGIC IACK6 IACK7
TS68000 CORE DATA BUS
The interrupt controller also receives external (EXRQ) requests. EXRQ interrupts are received by the IMP according to the operational mode selected. In the normal operational mode, EXRQ interrupts are encoded onto the IPL lines. In the dedicated operational mode, EXRQ interrupts are presented directly as IRQ7, IRQ6, and IRQ1. The interrupt controller block diagram is shown in Figure 28. The interrupt controller features are as follows: * * * * * Parallel I/O Ports two operational modes: normal and dedicated, eighteen priority-organized interrupt sources (internal and external), fully nested interrupt environment, unique vector number for each internal/external source, three selectable interrupt request/interrupt acknowledge pairs.
Port A and port B are two general-purpose I/O ports. Each pin in the 16-bit port A may be configured as a general-purpose I/O pin or as a dedicated peripheral interface pin. Port B has 12 pins. Eight pins may be configured as general-purpose pins or as dedicated peripheral interface pins, and four are general-purpose pins, each with interrupt capability.
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Dual-Port RAM The IMP has 1152 bytes of RAM configured as a dual-port memory. The RAM can be accessed by the internal RISC controller or one of three bus masters: the 68000 core, an external bus master, or the IDMA. All internal bus masters synchronously access the RAM with no wait states. External bus masters can access the RAM and registers synchronously or asynchronously. The RAM is divided into two parts. There are 576 bytes used as a parameter RAM, which includes pointers, counters, and registers for the serial ports. The other 576 bytes may be used for system RAM, which may include data buffers, or may be used for other purposes such as a no-wait-state cache.
Timers
There are three timer units. Two units are identical, general-purpose timers; the third unit can be used to implement a watchdog timer function. The two general-purpose timers are implemented with a timer mode register (TMR), a timer capture register (TCR), a timer counter (TCN), a timer reference register (TRR), and a timer event register (TER). The TMR contains the prescaler value programmed by the user. The watchdog timer, which has a TRR and TCN, uses a fixed prescaler value. The timer features are as follows: * Two general-purpose timer units: - maximum period of 16 seconds (at 16.67 MHz), - 60-nanosecond resolution (at 16.67 MHz), - programmable sources for the clock input, - input capture capability, - output compare with programmable mode for the output pin, - free run and restart modes. * One watchdog timer with a 16-bit counter and a reference register: - maximum period of 16 seconds (16.67 MHz), - 0.5-millisecond resolution (at 16 MHz), - output signal (WDOG), - interrupt capability.
External Chip-select Signals and Wait-state Logic
The TS68302 has a set of four programmable chip-select signals. Each chip select has an identical structure. For each memory area, an internally generated cycle-termination signal (DTACK) may be defined with up to six wait states to avoid using board space for cycle-termination logic. The four signals may each support four different classes of memory, such as high-speed static RAM, slower dynamic RAM, EPROM, and nonvolatile RAM. The chip-select and wait-state generation logic is active for all potential bus masters. The TS68302 has an on-chip clock generator which supplies internal and external highspeed clocks (up to 16.67 MHz). The clock circuitry uses three dedicated pins: EXTAL, XTAL, and CLKO.
Clock Generator
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System Control
The IMP system control consists of a system control register (SCR) containing bits for the following system control functions: * * * * * * * system status and control logic, bus arbitration logic with low interrupt latency, hardware watchdog, low power (standby) modes, disable CPU logic (68000), freeze control for debugging on-chip peripherals, AS control during read-modify-write cycles.
System Control Register
The SCR is a 32-bit register that consists of system status and control bits, a bus arbiter control bit, hardware watchdog control bits, low power control bits, and freeze select bits. The eight most significant bits of the SCR report events recognized by the system control logic and set the corresponding bit in the SCR. The low power modes are used, when no processing is required from the 68000/68008 core, to reduce the system power consumption to its minimum value. The low power modes may be exited by an interrupt from an on-chip peripheral.
Disable CPU Logic (68000)
This control allows an external processor direct connection to the bus and to the IMP's peripherals while the on-chip 68000 core is disabled. Entered during a system reset (RESET and HALT asserted together), this mode configures the IMP on-chip peripherals for use with other TS68032 units or other processors and is an effective configuration for systems needing more than three SCCs. This control is used to freeze the activity of selected peripherals and to debug systems. The IMP freezes its activity with no new interrupt requests, no memory accesses (internal or external), and no access of the serial channels. The IDMA controller completes any bus cycle in progress and releases bus ownership. No further bus cycles will be started as long as FRZ remains asserted.
Freeze Control
DRAM Refresh Controller The CP main (RISC) controller can optionally handle the dynamic RAM (DRAM) refresh
task without any intervention from the 68000 core. The refresh request can be generated from a TS68302 timer, baud rate generator, or externally. The DRAM refresh controller performs a standard 68000-type read cycle at programmable address sequences, with user-provided RAS and CAS generation.
Communications Processor
The CP in the TS68302 includes the main controller, six serial DMA channels, three SCCs, an SCP, and two SMCs. Host software configures each communications channel, as required by the application, to include parameters, baud rates, physical channel interfaces desired, and interrupting conditions. Buffer structures are set up for receive and transmit channels. Up to eight frames may be received or transmitted without host software involvement. Selection of the interrupt interface is also set by register bits in register space of the device. Data is transmitted and received using the appropriate buffer descriptors and buffer data space for a channel. The CP operates is a modified polling mode on each channel and buffer descriptor to identify buffers awaiting transmission and channels requiring servicing. The user sets a bit in the buffer descriptor of a transmit frame; when the CP polls and detects this bit, it will begin transmission. Generally, no other action is required to accomplish transmission.
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Main Controller The main controller is a microcode RISC processor that services all the serial channels. The main controller transfers data between the serial channels and internal/external RAM, executes host commands, and generates interrupts to the interrupt controller. Data is transferred from the serial channel to the dual-port RAM or to the external memory through the peripheral bus. If data is transferred between the SCC channels and external memory, the main controller uses up to six serial DMA channels for the transfer. The main controller also controls all character and address comparison and cyclic redundancy check (CRD) generation and checking. The execution unit includes the arithmetic logic unit (ALU), which performs arithmetic and logic operations on the registers. Serial Communication Controllers The TS68302 has three independent SCCs. Each SCC can be configured to implement different protocols - for example, to perform a gateway function or to interface to an ISDN basic rate channel. To simplify programming, each protocol implementation uses identical data structures. Five protocols are supported: high-level data link control (HDLC), binary synchronous communication (BISYNC), synchronous/asynchronous digital data communications message protocol (DDCMP), V.110, universal asynchronous receiver transmitter (UART), and a fully transparent mode. To aid system diagnostics, each SCC may be configured to operate in either an echo or loopback mode. In echo mode, the IMP retransmits any signals received; in loopback mode, the IMP locally receives signals originating from itself. The clock pins (RCLK, TCLK) for each SCC can be programmed for either an external or internal source, with user-programmable baud rates available for each SCC channel. Each SCC also supports the standard modem control signals: request to send (RTS), clear to send (CTS), and carrier detect (CD). Other modem signals may be provided through the parallel I/O pins. The SCC features are as follows: * * * * * * * * * * * * * * * * programmable baud rate generator driven by the internal or external clock, data may be clocked by the programmable baud rate generator or directly by an external clock, provides modem signals RTS, CTS, and CD, Full-duplex operation, Automatic echo mode, Local loopback mode, Baud rate generator outputs available externally. flexible data buffers with multiple buffers per frame allowed, separate interrupts for frames and buffers (receive and transmit), four address comparison registers with mask, maintenance of five 16-bit counters, flag/abort/idle generation/detection, zero insertion/deletion, NRZ/NRZI data encoding, 16-bit or 32-bit CRC-CCITT generation/checking, detection of non-octet aligned frames,
The SCC HDLC mode key features are as follows:
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
detection of frames that are too long, programmable 0 - 15 FLAGS between successive frames, automatic retransmission in case of collision. flexible data buffers, eight control recognition registers, automatic SYNC1 and SYNC2 detection, SYNC/DLE stripping and insertion, CRC-16 and LRC generation/checking, parity (VRC) generation/checking, supports BISYNC transparent operation (use of DLE characters), supports promiscuous (totally transparent) reception and transmission, maintains parity error counter, external SYNC support, reverse data mode. synchronous and asynchronous DDCMP links supported, flexible data buffers, four address comparison registers with mask, automatic frame synchronization, automatic message synchronization by searching for SOH, ENQ, or DLE, CRC-16 generation/checking, NRZ/NRZI data encoding, maintenance of four 16-bit error counters. provides synchronization and reception of 80-bit frames, automatic detection of framing errors, allows transmission of the 80-bit frame. flexible message-oriented data buffers, multidrop operation, receiver wakeup on idle line or address mode, eight control character comparison registers, two address comparison registers, four 16-bit error counters, programmable data length (7 - 8 bits), programmable 1 or 2 stop bits with fractional stop bits, even/odd/force/no parity generation, even/odd/no parity check, frame error, noise error, break, and idle detection, transmits idle and break sequences, freeze transmission option,
The SCC BISYNC mode key features are as follows:
The SCC DDCMP mode key features are as follows:
The SCC V.110 mode key features are as follows:
The SCC UART mode key features are as follows:
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* * * Serial Communication Port maintenance of four 16-bit error counters, provides asynchronous link over which DDCMP may be used, Flow control character transmission supported.
The SCP is a full-duplex, synchronous, character-oriented channel which provides a three-wire interface (TXD, RXD, and clock). The SCP consists of independent transmitter and receiver sections and a common SCP clock generator. The transmitter and receiver section use the same clock, which is derived from the main clock by an on-chip baud rate generator. The TS68302 is an SCP master, generating both the enable and the clock signals. The enable signals may be generated by the general-purpose I/O pins. The SCP allows the TS68302 to communicate with a variety of serial devices for the exchange of status and control information using a subset of the Motorola serial peripheral interface (SPI). Such devices may include industry-standard CODECs and other microcontrollers and peripherals. The SCP can be configured to operate in a local loopback mode, which is useful for diagnostic functions. The receiver and the transmitter operate normally in these modes. The SCP features are as follows: * * * * * three-wire interface (SPTXD, SPRXD, and SPCLK), full-duplex operation, clock rate up to 4.096 MHz, programmable baud rate generator, local loopback capability for testing purposes.
Serial Management Controllers
The SMCs are two synchronous, full-duplex ports that may be configured to operate in either IDL or GCI mode to handle the maintenance and control portions of these interfaces. The SMC ports are not used in PCM or NMSI modes. The SMC features are as follows: * * * * two modes of operation - IDL and GCI, local loopback capability for testing purposes, full-duplex operation, SMC1 in GCI mode detects collisions on the D channel.
Serial Channels Physical Interface
The serial channels physical interface connects the physical layer serial lines and the serial controllers (three SCCs and two SMCs). The interface implements both the routing and the time-division multiplexing for the full ISDN bandwidth. It supports four buses: IDL, GCI, PCM, and NMSI (a nonmultiplexed modem interface). The multiplexed modes (IDL, GCI, and PCM) also allow multiple channels (e.g., ISDN B channels) or userdefined subchannels to be assigned to a given SCC. The serial interface also supports two testing modes: echo and loopback. For the IDL and GSI buses, support of management functions in the frame structure is provided by the SCP or SMCs, respectively. Refer to Figure 29 for the serial channels physical interface block diagram.
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Figure 29. Serial Channels Physical Interface Block Diagram
TS68000 DATA BUS
SIMASK MASK REGISTER TO SMC1 TO SMC2
SIMODE MODE REGISTER TO SCC1 TO SCC2 TO SCC3
MUX
MUX
MUX
PHYSICAL INTERFACE BUS
CLOCKS
RXD
TXD
CTS
LAYER-1 BUS INTERFACE
L1SY1 L1RXD L1TXD L1GR L1RQ
RTS
TIME-SLOT ASSIGNER
L1CLK
ISDN INTERFACE OR SCC1
SCC2
SCC3
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TS68302
Preparation For Delivery
Packaging
Microcircuits are prepared for delivery in accordance with MIL-STD-1835.
Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 or Atmel standards and guaranteeing the parameters are tested at extreme temperatures for the entire temperature range.
Handling
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: a) Device should be handled on benches with conductive and grounded surfaces. b) Ground test equipment, tool and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50%, if practical.
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Package Mechanical Data
132-pin - Ceramic Pin Grid Array (in millimeter)
TOP VIEW 2.54 BSC 4.57 0.025 1.27 0.025 N M L K J 34.544 0.254 H G F E D C B A 1.27 0.127 34.544 0.254 2.667 0.254 2.54 BSC BOTTOM VIEW
1
3.17 0.635
2
3
4
5
6
7
8
9
10 11 12 13
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TS68302
132-pin - Ceramic Quad Flat Pack/CERQUAD
pin one ident S A D M D 0.1 (0.004) -T- SEATING PLANE R
CERQUAD132
VB L
G
Top view (window frame down)
DIM A B C D G H J K L R S V M J
Millimeters MIN MAX 21.85 22.86 21.85 22.86 3.94 4.52 0.204 0.292 0.64 BSC 1.0 0.5 0.13 0.20 0.51 0.76 20.32 REF 0.64 27.23 27.63 27.23 27.63 8 0
Inches MIN MAX 0.86 0.90 0.86 0.90 0.155 0.178 0.008 0.0115 0.025 BSC 0.019 0.039 0.005 0.008 0.020 0.030 0.800 REF 0.025 1.072 1.088 1.072 1.088 8 0
H
K C
Terminal Connections
132-pin - Ceramic Pin Grid Array 132-pin - Ceramic Quad Flat Pack/CERQUAD
See Figure 2.
See Figure 3.
Ordering Information
HI-REL Product
Commercial Atmel Part-Number TS68302MRB/C16 TS68302MAB/C16 TS68302DESC01QXC TS68302DESC01QYA Note: 1. Gullwing leads. Norms MIL-STD-883 MIL-STD-883 DESC DESC Package PGA 132 CERQUAD 132 PGA 132
(1) (1)
Temperature Range Tc (C) -55/+125 -55/+125 -55/+125 -55/+125
Frequency MHz 16.67 16.67 16.67 16.67
Drawing Number 5962-93159 5962-93159
CERQUAD 132
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Standard Product
Commercial Atmel Part-Number TS68302VR16 TS68302MR16 TS68302VA16 TS68302MA16 Note: 1. Gullwing leads. Norms Atmel Standard Atmel Standard Atmel Standard Atmel Standard Package PGA 132 PGA 132 CERQUAD 132(1) CERQUAD 132
(1)
Temperature Range Tc (C) -40/+85 -55/+125 -40/+85 -55/+125
Frequency MHz 16.67 16.67 16.67 16.67
Drawing Number Internal Internal Internal Internal
TS68302 M A
B/C 16
Type Temperature range: Tc M: -55, +125C V: -40, +85C C: 0, +70C
Speed (MHz) Screening level: ---- : Standard B/C: MIL-STD-883, class B B/T: Class B Screening according to MIL-STD-883 Hirel lead finish: --: Gold for PGA or Tinned for CERQUAD 1: Tinned for PGA
Package: R: Pin Grid Array 132 A: CERQUAD 132 (Gullwing leads)
Note: For availability of the different versions, contact your local Atmel sales office.
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
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